EP3C5E324A8ES View Datasheet(PDF) - Altera Corporation

Part Name

Description

Manufacturer

EP3C5E324A8ES

Cyclone III Device Handbook

Altera Corporation 

6–8

Chapter 6: I/O Features in the Cyclone III Device Family

OCT Support

On-Chip Series Termination with Calibration

The Cyclone III device family supports on-chip series termination with calibration in

all banks. The on-chip series termination calibration circuit compares the total

impedance of the output buffer to the external 25- ±1% or 50- ±1% resistors

connected to the RUP and RDN pins, and dynamically adjusts the output buffer

impedance until they match (as shown in Figure 6–2).

The RS shown in Figure 6–2 is the intrinsic impedance of the transistors that make up

the output buffer.

Figure 6–2. Cyclone III Device Family On-Chip Series Termination with Calibration

Cyclone III Device Family

Driver Series Termination

VCCIO

Receiving

Device

RS

ZO

RS

GND

OCT with calibration is achieved using the OCT calibration block circuitry. There is

one OCT calibration block in banks 2, 4, 5, and 7. Each calibration block supports each

side of the I/O banks. Because there are two I/O banks sharing the same calibration

block, both banks must have the same VCCIO if both banks enable OCT calibration. If

two related banks have different VCCIOs, only the bank in which the calibration block

resides can enable OCT calibration.

Cyclone III Device Handbook

Volume 1

July 2012 Altera Corporation

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