EP3C5E324A8ES View Datasheet(PDF) - Altera Corporation

Part Name

Description

Manufacturer

EP3C5E324A8ES

Cyclone III Device Handbook

Altera Corporation 

Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family

7–3

High-Speed I/O Interface

Table 7–1 lists which I/O bank supports these I/O standards in the Cyclone III device

family.

Table 7–1. Differential I/O Standards Supported in Cyclone III Device Family I/O Banks

Differential I/O Standards

I/O Bank Location

External Resistor

Network at

Transmitter

Transmitter (TX) Receiver (RX)

LVDS

1,2,5,6

Not Required

Yes

Yes

All

Three Resistors

RSDS

1,2,5,6

3, 4, 7, 8

All

Not Required

Three Resistors

Single Resistor

Yes

Not

Supported

mini-LVDS

1,2,5,6

All

Not Required

Three Resistors

Yes

Not

Supported

PPDS

1,2,5,6

All

Not Required

Three Resistors

Yes

Not

Supported

BLVDS (1)

All

Single Resistor

Yes

Yes

LVPECL (2)

All

NA

Not

Supported

Yes

Differential SSTL-2 (3)

All

NA

Yes

Yes

Differential SSTL-18 (3)

All

Differential HSTL-18 (3)

All

NA

Yes

Yes

NA

Yes

Yes

Differential HSTL-15 (3)

All

Differential HSTL-12 (3)

All

NA

Yes

Yes

NA

Yes

Yes

Notes to Table 7–1:

(1) Transmitter and Receiver FMAX depend on system topology and performance requirement.

(2) The LVPECL I/O standard is only supported on dedicated clock input pins.

(3) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input pins and PLL output clock

pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards.

You can use I/O pins and internal logic to implement a high-speed differential

interface in the Cyclone III device family. The Cyclone III device family does not

contain dedicated serialization or deserialization circuitry. Therefore, shift registers,

internal phase-locked loops (PLLs), and I/O cells are used to perform

serial-to-parallel conversions on incoming data and parallel-to-serial conversion on

outgoing data. The differential interface data serializers and deserializers (SERDES)

are automatically constructed in the core logic elements (LEs) with the Quartus® II

software ALTLVDS megafunction.

December 2011 Altera Corporation

Cyclone III Device Handbook

Volume 1

Share Link: