EP3C5E324A8ES View Datasheet(PDF) - Altera Corporation
Part Name
Description
Manufacturer
EP3C5E324A8ES Datasheet PDF : 274 Pages
| |||
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–39
Figure 9–17 shows the timing waveform for a PS configuration when using an
external host device as an external host.
Figure 9–17. PS Configuration Timing Waveform (1)
nCONFIG
tCF2ST1
tCFG
tCF2CK
nSTATUS (2)
CONF_DONE (3)
DCLK (4)
DATA[0]
tSTATUS
tCF2ST0
tCLK
tCF2CD
tCH tCL
tST2CK
tDH
Bit 0 Bit 1 Bit 2 Bit 3
tDSU
User I/O Tri-stated with internal pull-up resistor
INIT_DONE
Bit n
(5)
User Mode
tCD2UM
Notes to Figure 9–17:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE
are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
(2) After power-up, the Cyclone III device family holds nSTATUS low during POR delay.
(3) After power-up, before and during configuration, CONF_DONE is low.
(4) In user mode, drive DCLK either high or low when using the PS configuration scheme, whichever is more convenient.
When using the AS configuration scheme, DCLK is a Cyclone III device family output pin and must not be driven
externally.
(5) Do not leave the DATA[0] pin floating after configuration. Drive it high or low, whichever is more convenient.
Table 9–13 lists the PS configuration timing parameters for Cyclone III device family.
Table 9–13. PS Configuration Timing Parameters for Cyclone III Device Family (Part 1 of 2)
Symbol
Parameter
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
tCF2CK
tST2CK
tDSU
tDH
tCH
tCL
tCLK
fMAX
tCD2UM
tCD2CU
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency
CONF_DONE high to user mode (3)
CONF_DONE high to CLKUSR enabled
Minimum
—
—
500
45
—
800 (1)
2
5
0
3.2
3.2
7.5
—
300
4 × maximum DCLK period
Maximum Unit
500
ns
500
ns
—
ns
800 (1)
s
800 (2)
s
—
s
—
s
—
ns
—
ns
—
ns
—
ns
—
ns
100 (4)
MHz
650
s
—
—
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
Share Link: 