EP3C5E324A8ES View Datasheet(PDF) - Altera Corporation
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EP3C5E324A8ES Datasheet PDF : 274 Pages
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–47
FPP Configuration Timing
Figure 9–23 shows the timing waveform for FPP configuration when using an
external host.
Figure 9–23. FPP Configuration Timing Waveform (1)
nCONFIG
tCF2ST1
tCFG
tCF2CK
nSTATUS (2)
CONF_DONE (3)
DCLK
DATA[7..0]
tSTATUS
tCF2ST0
tCLK
tCF2CD
tCH tCL
tST2CK
tDH
Byte 0 Byte 1
tDSU
Byte 2
Byte 3
User I/O Tri-stated with internal pull-up resistor
INIT_DONE
Byte n-1 Byte n
(4)
(5)
User Mode
User Mode
tCD2UM
Notes to Figure 9–23:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE
are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
(2) After power-up, the Cyclone III device family holds nSTATUS low during POR delay.
(3) After power-up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. It must be driven high or low, whichever is more convenient.
(5) DATA[7..0] is available as user I/O pin after configuration; the state of the pin depends on the dual-purpose pin
settings.
Table 9–14 lists the FPP configuration timing parameters for Cyclone III device family.
Table 9–14. FPP Timing Parameters for Cyclone III Device Family (Part 1 of 2)
Symbol
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
tCF2CK
tST2CK
tDSU
tDH
tCH
tCL
tCLK
fMAX
tCD2UM
Parameter
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
DATA setup time before rising edge on DCLK
DATA hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency
CONF_DONE high to user mode (2)
Minimum
—
—
500
45
—
230 (1)
2
5
0
3.2
3.2
7.5
—
300
Maximum Unit
500
ns
500
ns
—
ns
230 (1)
s
230 (1)
s
—
s
—
s
—
ns
—
ns
—
ns
—
ns
—
ns
100 (3)
MHz
650
s
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
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