EP3C5E324A8ES View Datasheet(PDF) - Altera Corporation

Part Name

Description

Manufacturer

EP3C5E324A8ES

Cyclone III Device Handbook

Altera Corporation 

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

PLL Cascading

5–25

Figure 5–19 shows using GCLK while cascading PLLs.

Figure 5–19. PLL Cascading Using GCLK

Output from PLL

Five Clock

Control Blocks

Input to PLL

CLK[8..11]

4

PLL

2

3

5

2

PLL

2

1

Remote clock

from two Clock 2

pins at adjacent

edge of device

CLK[0..3]

Five Clock 4

Control Blocks

2

5

Output from PLL

20 GCLK[10..14]

GCLK[0:19]

GCLK[0..4]

20 GCLK[0:19]

1

1

GCLK[0:19] 20

GCLK[5..9]

GCLK[0:19]

GCLK[15..19] 20

1

Output from PLL

5

2

Five Clock

Control Blocks

4

CLK[4..7]

2

PLL

1

2

5

PLL

2

4

4

CLK[12..15]

Five Clock

Control Blocks

Output from PLL

Consider the following guidelines when cascading PLLs:

■ Set the primary PLL to low bandwidth to help filter jitter. Set the secondary PLL to

high bandwidth to be able to track the jitter from the primary PLL. You can view

the Quartus II software compilation report file to ensure the PLL bandwidth

ranges do not overlap. If the bandwidth ranges overlap, jitter peaking can occur in

the cascaded PLL scheme.

1 You can get an estimate of the PLL deterministic jitter and static phase error

(SPE) by using the TimeQuest Timing Analyzer in the Quartus II software.

Use the SDC command "derive_clock_uncertainty" to direct TimeQuest to

generate a report titled "PLLJ_PLLSPE_INFO.txt" in your project directory.

Then, use "set_clock_uncertainty" commands to add jitter and SPE values to

your clock constraints.

July 2012 Altera Corporation

Cyclone III Device Handbook

Volume 1

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