Memory and register map
STM8S005K6 STM8S005C6
Address
0x00 50B3
Block Register label Register name
RST RST_SR
Reset status register
Reset status
0xXX(1)
0x00 50B4 to
0x00 50BF
Reserved area (12 bytes)
0x00 50C0
CLK CLK_ICKR
Internal clock control register
0x01
0x00 50C1
CLK_ECKR
External clock control register
0x00
0x00 50C2
Reserved area (1 byte)
0x00 50C3
CLK CLK_CMSR
Clock master status register
0xE1
0x00 50C4
CLK_SWR
Clock master switch register
0xE1
0x00 50C5
CLK_SWCR
Clock switch control register
0xXX
0x00 50C6
CLK_CKDIVR Clock divider register
0x18
0x00 50C7
CLK_PCKENR1 Peripheral clock gating register 1
0xFF
0x00 50C8
CLK_CSSR
Clock security system register
0x00
0x00 50C9
CLK_CCOR
Configurable clock control register
0x00
0x00 50CA
CLK_PCKENR2 Peripheral clock gating register 2
0xFF
0x00 50CC
CLK_HSITRIMR HSI clock calibration trimming register 0x00
0x00 50CD
CLK_SWIMCCR SWIM clock control register
0bXXXX
XXX0
0x00 50CE to
0x00 50D0
Reserved area (3 bytes)
0x00 50D1
WWDG WWDG_CR
WWDG control register
0x7F
0x00 50D2
WWDG_WR
WWDR window register
0x7F
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DocID022186 Rev 3