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PIC16F917-E/ML View Datasheet(PDF) - Microchip Technology

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Description
Manufacturer
PIC16F917-E/ML Datasheet PDF : 330 Pages
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PIC16F913/914/916/917/946
FIGURE 16-8:
INT PIN INTERRUPT TIMING
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT(3)
(4)
INT pin
INTF Flag
(1)
(INTCON reg.)
(1)
(5)
GIE bit
(INTCON reg.)
Interrupt Latency (2)
Instruction Flow
PC
Instruction
Fetched
PC
Inst (PC)
PC + 1
Inst (PC + 1)
PC + 1
0004h
Inst (0004h)
0005h
Inst (0005h)
Instruction
Executed
Inst (PC - 1)
Inst (PC)
Dummy Cycle
Dummy Cycle
Inst (0004h)
Note 1:
2:
3:
4:
5:
INTF flag is sampled here (every Q1).
Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
CLKOUT is available only in INTOSC and RC Oscillator modes.
For minimum width of INT pulse, refer to AC specifications in Section 19.0 “Electrical Specifications”.
INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 16-6: SUMMARY OF INTERRUPT REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Value on all
POR, BOR other Resets
INTCON
PIR1
PIR2
PIE1
PIE2
Legend:
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000x
EEIF
ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
OSFIF C2IF
C1IF LCDIF
LVDIF
CCP2IF 0000 -0-0 0000 -0-0
EEIE
ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
OSFIE C2IE
C1IE LCDIE
LVDIE
CCP2IE 0000 -0-0 0000 -0-0
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by the Interrupt
Module.
DS41250F-page 232
© 2007 Microchip Technology Inc.

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