PIC16F914-E/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F914-E/ML

28/40/44/64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

Microchip Technology 

PIC16F913/914/916/917/946

TABLE 19-16: I2C™ BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min.

Max. Units

Conditions

100*

101*

102*

103*

90*

91*

106*

107*

92*

109*

110*

*

Note 1:

2:

THIGH

Clock high time

400 kHz mode

SSP Module

0.6

—

μs Device must operate at a

1.5TCY

—

minimum of 10 MHz

TLOW

Clock low time

400 kHz mode

SSP Module

1.3

—

μs Device must operate at a

1.5TCY

—

minimum of 10 MHz

TR

SDA and SCL rise 400 kHz mode

20 + 0.1CB 250

ns CB is specified to be from

time

10-400 pF

TF

SDA and SCL fall time 400 kHz mode

20 + 0.1CB 250

ns CB is specified to be from

10-400 pF

TSU:STA

Start condition setup 400 kHz mode

time

1.3

—

μs Only relevant for Repeated

Start condition

THD:STA Start condition hold

time

400 kHz mode

0.6

—

μs After this period the first clock

pulse is generated

THD:DAT Data input hold time 400 kHz mode

0

0.9

μs

TSU:DAT Data input setup time 400 kHz mode

100

—

ns (Note 2)

TSU:STO

Stop condition setup 400 kHz mode

time

0.6

—

μs

TAA

Output valid from

400 kHz mode

clock

—

—

ns (Note 1)

TBUF

Bus free time

400 kHz mode

1.3

—

μs Time the bus must be free

before a new transmission

can start

CB

Bus capacitive loading

—

400 pF

These parameters are characterized but not tested.

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)

of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement

TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of

the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA

line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL

line is released.

DS41250F-page 282

© 2007 Microchip Technology Inc.

Share Link: