PIC16F913/914/916/917/946
TABLE 2-3: PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 2
100h INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 41,226
101h TMR0
Timer0 Module Register
xxxx xxxx 99,226
102h PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 40,226
103h STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 32,226
104h FSR
Indirect Data Memory Address Pointer
xxxx xxxx 41,226
105h WDTCON
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 235,227
106h PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0 xxxx xxxx 54,226
107h LCDCON
LCDEN SLPEN WERR VLCDEN
CS1
CS0
LMUX1 LMUX0 0001 0011 145,227
108h LCDPS
WFT BIASMD LCDA
WA
LP3
LP2
LP1
LP0 0000 0000 146,227
109h LVDCON
—
—
IRVST LVDEN
—
LVDL2
LVDL1
LVDL0 --00 -100 145,228
10Ah PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter ---0 0000 40,226
10Bh INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 34,226
10Ch EEDATL
EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 0000 0000 188,228
10Dh EEADRL
EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 0000 0000 188,228
10Eh EEDATH
—
—
EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 188,228
10Fh EEADRH
—
—
—
EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---0 0000 188,228
110h LCDDATA0
SEG7
COM0
SEG6
COM0
SEG5
COM0
SEG4
COM0
SEG3
COM0
SEG2
COM0
SEG1
COM0
SEG0 xxxx xxxx 147,228
COM0
111h LCDDATA1
112h LCDDATA2(2)
SEG15
COM0
SEG23
COM0
SEG14
COM0
SEG22
COM0
SEG13
COM0
SEG21
COM0
SEG12
COM0
SEG20
COM0
SEG11
COM0
SEG19
COM0
SEG10
COM0
SEG18
COM0
SEG9
COM0
SEG17
COM0
SEG8
COM0
SEG16
COM0
xxxx xxxx
xxxx xxxx
147,228
147,228
113h LCDDATA3
SEG7
COM1
SEG6
COM1
SEG5
COM1
SEG4
COM1
SEG3
COM1
SEG2
COM1
SEG1
COM1
SEG0 xxxx xxxx 147,228
COM1
114h LCDDATA4
115h LCDDATA5(2)
SEG15
COM1
SEG23
COM1
SEG14
COM1
SEG22
COM1
SEG13
COM1
SEG21
COM1
SEG12
COM1
SEG20
COM1
SEG11
COM1
SEG19
COM1
SEG10
COM1
SEG18
COM1
SEG9
COM1
SEG17
COM1
SEG8
COM1
SEG16
COM1
xxxx xxxx
xxxx xxxx
147,228
147,228
116h LCDDATA6
SEG7
COM2
SEG6
COM2
SEG5
COM2
SEG4
COM2
SEG3
COM2
SEG2
COM2
SEG1
COM2
SEG0 xxxx xxxx 147,228
COM2
117h LCDDATA7
118h LCDDATA8(2)
SEG15
COM2
SEG23
COM2
SEG14
COM2
SEG22
COM2
SEG13
COM2
SEG21
COM2
SEG12
COM2
SEG20
COM2
SEG11
COM2
SEG19
COM2
SEG10
COM2
SEG18
COM2
SEG9
COM2
SEG17
COM2
SEG8
COM2
SEG16
COM2
xxxx xxxx
xxxx xxxx
147,228
147,228
119h LCDDATA9
SEG7
COM3
SEG6
COM3
SEG5
COM3
SEG4
COM3
SEG3
COM3
SEG2
COM3
SEG1
COM3
SEG0 xxxx xxxx 147,228
COM3
11Ah LCDDATA10
11Bh LCDDATA11(2)
11Ch
11Dh
11Eh
LCDSE0(3)
LCDSE1(3)
LCDSE2(2,3)
SEG15
COM3
SEG23
COM3
SE7
SE15
SE23
SEG14
COM3
SEG22
COM3
SE6
SE14
SE22
SEG13
COM3
SEG21
COM3
SE5
SE13
SE21
SEG12
COM3
SEG20
COM3
SE4
SE12
SE20
SEG11
COM3
SEG19
COM3
SE3
SE11
SE19
SEG10
COM3
SEG18
COM3
SE2
SE10
SE18
SEG9
COM3
SEG17
COM3
SE1
SE9
SE17
SEG8
COM3
SEG16
COM3
SE0
SE8
SE16
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
147,228
147,228
147,228
147,228
147,228
11Fh
—
Unimplemented
—
—
Legend:
Note 1:
2:
3:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
PIC16F914/917 and PIC16F946 only.
This register is only initialized by a POR or BOR reset and is unchanged by other Resets.
DS41250F-page 30
© 2007 Microchip Technology Inc.