PIC16F913/914/916/917/946
3.2.1.8 RA7/OSC1/CLKIN/T1OSI
Figure 3-8 shows the diagram for this pin. The RA7 pin
is configurable to function as one of the following:
• a general purpose I/O
• a crystal/resonator connection
• a clock input
• a Timer1 oscillator connection
FIGURE 3-8:
BLOCK DIAGRAM OF RA7
Data Bus
WR PORTA
To OSC2 Oscillator
Circuit
D
Q
CK Q
Data Latch
WR TRISA
FOSC = 10x
D
Q
CK Q
TRIS Latch
RD TRISA
FOSC = 011
VDD
FOSC = 10x
TTL
Input Buffer
I/O Pin
VSS
RD PORTA
TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
ADCON0
ADFM VCFG1 VCFG0 CHS2
CHS1
CHS0 GO/DONE ADON 0000 0000
ANSEL
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0 1111 1111
CMCON0
CONFIG(1)
C2OUT
CPD
C1OUT
CP
C2INV
MCLRE
C1INV
PWRTE
CIS
WDTE
CM2
FOSC2
CM1
FOSC1
CM0
FOSC0
0000 0000
—
OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
LCDCON
LCDEN SLPEN WERR VLCDEN
CS1
CS0
LMUX1 LMUX0 0001 0011
LCDSE0
SE7
SE6
SE5
SE4
SE3
SE2
SE1
SE0
0000 0000
LCDSE1
SE15
SE14
SE13
SE12
SE11
SE10
SE9
SE8
0000 0000
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx xxxx
SSPCON
WCOL SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000
T1CON
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: See Configuration Word register (CONFIG) for operation of all register bits.
Value on all
other Resets
0000 0000
1111 1111
0000 0000
—
1111 1111
0001 0011
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
1111 1111
DS41250F-page 52
© 2007 Microchip Technology Inc.