TDA7385_01 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
TDA7385_01 Datasheet PDF : 12 Pages
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Figure 9: Output Noise vs. Source Resistance
TDA7385
Figure 10: Power Dissipation & Efficiency vs.
Output Power
Ptot (W)
Ptot
Rg (Ω)
APPLICATION HINTS (ref. to the circuit of fig. 1)
BIASING AND SVR
As shown by fig. 11, all the TDA7385’s main sec-
tions, such as INPUTS, OUTPUTS AND AC-GND
(pin 16) are internally biased at half Supply Volt-
age level (Vs/2), which is derived from the Supply
Voltage Rejection (SVR) block. In this way no cur-
rent flows through the internal feedback network.
The AC-GND is common to all the 4 amplifiers
and represents the connection point of all the in-
verting inputs.
Both individual inputs and AC-GND are con-
nected to Vs/2 (SVR) by means of 100KΩ resis-
tors.
Figure 11: Input/Output Biasing.
100KΩ
0.1µF
C1 ÷ C4
IN
To ensure proper operation and high supply volt-
age rejection, it is of fundamental importance to
provide a good impedance matching between IN-
PUTS and AC-GROUND terminations. This im-
plies that C1, C2, C3, C4, C5 CAPACITORS HAVE
TO CARRY THE SAME NOMINAL VALUE AND
THEIR TOLERANCE SHOULD NEVER EXCEED
±10 %.
Besides its contribution to the ripple rejection, the
SVR capacitor governs the turn ON/OFF time se-
quence and, consequently, plays an essential role
in the pop optimization during ON/OFF transients.
To conveniently serve both needs, ITS MINIMUM
RECOMMENDED VALUE IS 10µF.
+
-
8KΩ
400Ω
VS
10KΩ
70KΩ SVR
10KΩ
100KΩ
47µF
C6
400Ω
AC_GND
8KΩ
-
+
0.1µF
C5
D95AU302
TOWARDS
OTHER CHANNELS
7/12
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