PIC16F54T-I/SO View Datasheet(PDF) - Microchip Technology
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Description
Manufacturer
PIC16F54T-I/SO Datasheet PDF : 88 Pages
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PIC16F5X
7.0 TIMER0 MODULE AND TMR0
REGISTER
The Timer0 module has the following features:
• 8-bit Timer/Counter register, TMR0
- Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 7-2 and Figure 7-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
incrementing edge is determined by the source edge
select bit T0SE (OPTION<4>). Clearing the T0SE bit
selects the rising edge. Restrictions on the external
clock input are discussed in detail in Section 7.1
“Using Timer0 with an External Clock”.
Note:
The prescaler may be used by either the
Timer0 module or the Watchdog Timer, but
not both.
The prescaler assignment is controlled in software by
the control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 7.2 “Prescaler” details
the operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 7-1.
FIGURE 7-1:
TIMER0 BLOCK DIAGRAM
FOSC/4
T0CKI
pin
T0SE(1)
Data Bus
0
PSout
8
1
Sync with
1
Internal
TMR0 Reg
Programmable 0
Prescaler(2)
Clocks
PSout
(2 cycle delay) Sync
3
PS2, PS1, PS0(1)
T0CS(1)
PSA(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in Section 3.4 “Option Register”.
2: The prescaler is shared with the Watchdog Timer (Figure 7-5).
FIGURE 7-2:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER
PC
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter)
PC - 1
PC
PC + 1
PC + 2
PC + 3
PC + 4
PC + 5
PC + 6
Instruction
Fetch
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Timer0
T0
Instruction
Executed
T0 + 1
T0 + 2
NT0
NT0
NT0
NT0 + 1
NT0 + 2
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0 Read TMR0
reads NT0 + 1 reads NT0 + 2
© 2007 Microchip Technology Inc.
DS41213D-page 33
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