ST7PLIT110BF0M3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PLIT110BF0M3

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI

STMicroelectronics 

ST7LITE1xB

13.11 10-BIT ADC CHARACTERISTICS

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ 1)

Max

fADC

VAIN

RAIN

CADC

tSTAB

tADC

ADC clock frequency

Conversion voltage range 2)

External input resistor

Internal sample and hold capacitor

Stabilization time after ADC enable

Conversion time (Sample+Hold)

- Sample capacitor loading time

- Hold conversion time

fCPU=8MHz, fADC=4MHz

VSSA

4

VDDA

10 3)

6

0 4)

3.5

4

10

Analog Part

1

IADC Digital Part

0.2

Figure 110. Typical Application with ADC

VDD

Unit

MHz

V

kΩ

pF

µs

1/fADC

mA

VAIN

RAIN

AINx

VT

0.6V

VT

0.6V

IL

±1μA

10-Bit A/D

Conversion

CADC

6pF

ST72XXX

Notes:

1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-

lines and are not tested.

2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.

3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data

based on characterization results, not tested in production.

4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then

always valid.

Related application notes:

Understanding and minimizing ADC conversion errors (AN1636)

Software techniques for compensating ST7 ADC errors (AN1711)

139/159

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