ST7PLIT110BY0M3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PLIT110BY0M3

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI

STMicroelectronics 

ST7LITE1xB

POWER SAVING MODES (Cont’d)

9.4.1 Halt Mode Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

– When using an external interrupt to wake up the

microcontroller, re-initialize the corresponding I/

O as “Input Pull-up with Interrupt” before execut-

ing the HALT instruction. The main reason for

this is that the I/O may be wrongly configured

due to external interference or by an unforeseen

logical condition.

– For the same reason, re-initialize the level sensi-

tiveness of each external interrupt as a precau-

tionary measure.

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a

program counter failure, it is advised to clear all

occurrences of the data value 0x8E from memo-

ry. For example, avoid defining a constant in pro-

gram memory with the value 0x8E.

– As the HALT instruction clears the interrupt mask

in the CC register to allow interrupts, the user

may choose to clear all pending interrupt bits be-

fore executing the HALT instruction. This avoids

entering other peripheral interrupt routines after

executing the external interrupt routine corre-

sponding to the wake-up event (reset or external

interrupt).

9.5 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power con-

sumption mode of the MCU with a real time clock

available. It is entered by executing the ‘HALT’ in-

struction. The decision to enter either in ACTIVE-

HALT or HALT mode is given by the LTCSR/ATC-

SR register status as shown in the following table:

LTCSR1

TB1IE bit

ATCSR

OVFIE

bit

ATCSR

CK1 bit

ATCSR

CK0 bit

Meaning

0

x

x

0 ACTIVE-HALT

0

0

x

x mode disabled

1

x

x

x ACTIVE-HALT

x

1

0

1 mode enabled

The MCU can exit ACTIVE-HALT mode on recep-

tion of a specific interrupt (see Table 5, “Interrupt

Mapping,” on page 37) or a RESET.

– When exiting ACTIVE-HALT mode by means of

a RESET, a 256 or 4096 CPU cycle delay oc-

curs. After the start up delay, the CPU resumes

operation by fetching the reset vector which

woke it up (see Figure 28).

– When exiting ACTIVE-HALT mode by means of

an interrupt, the CPU immediately resumes oper-

ation by servicing the interrupt vector which woke

it up (see Figure 28).

When entering ACTIVE-HALT mode, the I bit in

the CC register is cleared to enable interrupts.

Therefore, if an interrupt is pending, the MCU

wakes up immediately (see Note 3).

In ACTIVE-HALT mode, only the main oscillator

and the selected timer counter (LT/AT) are running

to keep a wake-up time base. All other peripherals

are not clocked except those which get their clock

supply from another clock generator (such as ex-

ternal or auxiliary oscillator).

Note: As soon as ACTIVE-HALT is enabled, exe-

cuting a HALT instruction while the Watchdog is

active does not generate a RESET.

This means that the device cannot spend more

than a defined delay in this power saving mode.

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