ST7PLIT110BF0M3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PLIT110BF0M3

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI

STMicroelectronics 

ST7LITE1xB

POWER SAVING MODES (Cont’d)

Figure 31. AWUFH Mode Flow-chart

HALT INSTRUCTION

(Active-Halt disabled)

(AWUCSR.AWUEN=1)

WDGHALT 1)

1

WATCHDOG

RESET

ENABLE

0

WATCHDOG

DISABLE

AWU RC OSC ON

MAIN OSC

OFF

PERIPHERALS 2) OFF

CPU

OFF

I[1:0] BITS

10

N

RESET

N

Y

INTERRUPT 3)

AWU RC OSC OFF

Y

MAIN OSC

ON

PERIPHERALS OFF

CPU

ON

I[1:0] BITS

XX 4)

256 OR 4096 CPU CLOCK

CYCLE DELAY5)

AWU RC OSC

MAIN OSC

PERIPHERALS

CPU

I[1:0] BITS

OFF

ON

ON

ON

XX 4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source

can still be active.

3. Only an AWUFH interrupt and some specific in-

terrupts can exit the MCU from HALT mode (such

as external interrupt). Refer to Table 5, “Interrupt

Mapping,” on page 37 for more details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg-

ister are set to the current software priority level of

the interrupt routine and recovered when the CC

register is popped.

5. If the PLL is enabled by option byte, it outputs

the clock after an additional delay of tSTARTUP (see

Figure 13).

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