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ST7PLIT115BF1B6TR View Datasheet(PDF) - STMicroelectronics

Part Name
Description
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ST7PLIT115BF1B6TR Datasheet PDF : 159 Pages
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ST7LITE1xB
LITE TIMER (Cont’d)
Bit 6 = ICF Input Capture Flag
This bit is set by hardware and cleared by software
by reading the LTICR register. Writing to this bit
does not change the bit value.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialize
the ICF bit by reading the LTICR register
Bit 5 = TB Timebase period selection
This bit is set and cleared by software.
0: Timebase period = tOSC * 8000 (1ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2ms @ 8
MHz)
Bit 4 = TB1IE Timebase Interrupt enable
This bit is set and cleared by software.
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled
Bit 3 = TB1F Timebase Interrupt Flag
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
0: No counter overflow
1: A counter overflow has occurred
Bits 2:0 = Reserved
LITE TIMER INPUT CAPTURE
(LTICR)
Read only
Reset Value: 0000 0000 (00h)
REGISTER
7
0
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Bits 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by
hardware after a reset. If the ICF bit in the LTCSR
is cleared, the value of the 8-bit up-counter will be
captured when a rising or falling edge occurs on
the LTIC pin.
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