ST7LITE1xB
Pin No.
Pin Name
Level
Port / Control
Input
Output
Main
Function
(after
reset)
Alternate Function
12
10
10
PA6 /MCO/
ICCCLK/BREAK
I/O
CT
X
ei1
13
11
11
PA5 /ICCDATA/
ATPWM3
I/O CT HS X
ei1
14 12 12 PA4/ATPWM2 I/O CT HS X
15 13 - PA3/ATPWM1 I/O CT HS X
16 14 13 PA2/ATPWM0
17 15 - PA1/ATIC
I/O CT HS X
ei0
I/O CT HS X
18 16 14 PA0/LTIC
I/O CT HS X
19 17 15 OSC2/PC1
I/O
X
20 18 16 OSC1/CLKIN/PC0 I/O
X
X X Port A6
X X Port A5
X X Port A4
Main Clock Output or In Circuit
Communication Clock or External
BREAK
Caution: During normal operation
this pin must be pulled- up, inter-
nally or externally (external pull-up
of 10k mandatory in noisy environ-
ment). This is to avoid entering ICC
mode unexpectedly during a reset.
In the application, even if the pin is
configured as output, any reset will
put it back in input pull-up
In Circuit Communication Data or
Auto-Reload Timer PWM3
Auto-Reload Timer PWM2
X X Port A3 Auto-Reload Timer PWM1
X X Port A2 Auto-Reload Timer PWM0
X X Port A1 Auto-Reload Timer Input Capture
X X Port A0 Lite Timer Input Capture
X Port C13)
X Port C03)
Resonator oscillator inverter out-
put
Resonator oscillator inverter input
or External clock input
Notes:
1. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA
pins to ground.
2. When the pin is configured as analog input, positive and negative current injections are not allowed.
3. PCOR not implemented but p-transistor always active in output mode (refer to Figure 32 on page 50).
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