ST7PLIT115BF1M3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PLIT115BF1M3

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI

STMicroelectronics 

ST7LITE1xB

10-BIT A/D CONVERTER (ADC) (Cont’d)

11.5.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR)

Read/Write (Except bit 7 read only)

Reset Value: 0000 0000 (00h)

7

0

EOC SPEED ADON 0

0 CH2 CH1 CH0

Bit 7 = EOC End of Conversion

This bit is set by hardware. It is cleared by hard-

ware when software reads the ADCDRH register

or writes to any bit of the ADCCSR register.

0: Conversion is not complete

1: Conversion complete

Bit 6 = SPEED ADC clock selection

This bit is set and cleared by software. It is used

together with the SLOW bit to configure the ADC

clock speed. Refer to the table in the SLOW bit de-

scription (ADCDRL register).

Bit 5 = ADON A/D Converter on

This bit is set and cleared by software.

0: A/D converter and amplifier are switched off

1: A/D converter and amplifier are switched on

Bits 4:3 = Reserved. Must be kept cleared.

Bits 2:0 = CH[2:0] Channel Selection

These bits are set and cleared by software. They

select the analog input to convert.

Channel Pin*

CH2 CH1 CH0

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

*The number of channels is device dependent. Refer to

the device pinout description.

DATA REGISTER HIGH (ADCDRH)

Read Only

Reset Value: xxxx xxxx (xxh)

7

0

D9 D8 D7 D6 D5 D4 D3 D2

Bits 7:0 = D[9:2] MSB of Analog Converted Value

AMP CONTROL/DATA REGISTER LOW (AD-

CDRL)

Read / Write

Reset Value: 0000 00xx (0xh)

7

0

0

0

0

AMP

CAL

SLOW

AMP-

SEL

D1

D0

Bits 7:5 = Reserved. Forced by hardware to 0.

Bit 4 = AMPCAL Amplifier Calibration Bit

This bit is set and cleared by software. It is advised

to use this bit to calibrate the ADC when amplifier

is ON. Setting this bit internally connects amplifier

input to 0V. Hence, corresponding ADC output can

be used in software to eliminate amplifier-offset er-

ror.

0: Calibration off

1: Calibration on. (The input voltage of the amplifi-

er is set to 0V)

Bit 3 = SLOW Slow mode

This bit is set and cleared by software. It is used

together with the SPEED bit in the ADCCSR regis-

ter to configure the ADC clock speed as shown on

the table below.

fADC

SLOW SPEED

fCPU/2

fCPU

fCPU/4

0

0

0

1

1

x

Note: max fADC allowed = 4MHz (see section

13.11 on page 139)

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