PSD4221F1-15UI View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD4221F1-15UI

Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

STMicroelectronics 

PSD4235G2

ment 0. You can see that half of the primary Flash

memory segment 0 and one-fourth of secondary

Flash memory segment 0 cannot be accessed in

this example. Also note that an equation that de-

fined FS1 to anywhere in the range of 8000h to

BFFFh would not be valid.

Figure 8 shows the priority levels for all memory

components. Any component on a higher level can

overlap and has priority over any component on a

lower level. Components on the same level must

not overlap. Level 1 has the highest priority and

level 3 has the lowest.

Memory Select Configuration for MCUs with

Separate Program and Data Spaces. The

80C51XA and compatible family of MCUs, can be

configured to have separate address spaces for

Program memory (selected using Program Select

Enable (PSEN, CNTL2)) and Data memory (se-

lected using Read Strobe (RD, CNTL1)). Any of

the memories within the PSD can reside in either

space or both spaces. This is controlled through

manipulation of the VM register that resides in the

CSIOP space.

The VM register is set using PSDsoft Express to

have an initial value. It can subsequently be

changed by the MCU so that memory mapping

can be changed on-the-fly.

For example, you may wish to have SRAM and pri-

mary Flash memory in the Data space at Boot-up,

and secondary Flash memory in the Program

space at Boot-up, and later swap the secondary

Flash memory and primary Flash memory. This is

easily done with the VM register by using PSDsoft

Express to configure it for Boot-up and having the

MCU change it when desired.

Table 25 describes the VM Register.

Separate Space Modes. Program space is sep-

arated from Data space. For example, Program

Select Enable (PSEN, CNTL2) is used to access

the program code from the primary Flash memory,

while Read Strobe (RD, CNTL1) is used to access

data from the secondary Flash memory, SRAM

and I/O Port blocks. This configuration requires

the VM register to be set to 0Ch (see Figure 9).

Figure 9. 8031 Memory Modules – Separate Space

DPLD

RS0

CSBOOT0-3

FS0-FS7

PSEN

RD

Primary

Flash

Memory

CS

OE

Combined Space Modes. The Program and

Data spaces are combined into one memory

space that allows the primary Flash memory, sec-

ondary Flash memory, and SRAM to be accessed

by either Program Select Enable (PSEN, CNTL2)

or Read Strobe (RD, CNTL1). For example, to

Secondary

Flash

Memory

CS

OE

SRAM

CS

OE

AI02869C

configure the primary Flash memory in Combined

space, bits 2 and 4 of the VM register are set to 1

(see Figure 10).

80C51XA Memory Map Example. See the Ap-

plication Notes for examples.

29/89

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