PSD4203F3-15UI View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD4203F3-15UI

Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

STMicroelectronics 

PSD4235G2

DECODE PLD (DPLD)

The DPLD, shown in Figure 13, is used for decod-

ing the address for internal and external compo-

nents. The DPLD can be used to generate the

following decode signals:

s 8 Sector Select (FS0-FS7) signals for the

primary Flash memory (three product terms

each)

s 4 Sector Select (CSBOOT0-CSBOOT3) signals

for the secondary Flash memory (three product

terms each)

s 1 internal SRAM Select (RS0) signal (three

product terms)

s 1 internal CSIOP Select (PSD Configuration

Register) signal

s 1 JTAG Select signal (enables JTAG-ISP on

Port E)

s 2 internal Peripheral Select signals

(Peripheral I/O mode).

Figure 13. DPLD Logic Array

3

3

3

3

(INPUTS)

3

I /O PORTS (PORT A,B,F)

(32)

3

MCELLAB.FB [7:0] (FEEDBACKS)

(8)

3

MCELLBC.FB [7:0] (FEEDBACKS)

(8)

3

PGR0 -PGR7

(8)

3

A[15:0] *

(16)

3

PD[3:0] (ALE,CLKIN,CSI)

(4)

3

PDN (APD OUTPUT)

(1)

3

CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) (3)

RESET

(1)

3

RD_BSY

(1)

1

1

1

1

Note: 1. The address inputs are A19-A4 when in 80C51XA mode

2. Additional address lines can be brought ino the PSD via Port A, B, C, D, or F.

CSBOOT 0

CSBOOT 1

CSBOOT 2

CSBOOT 3

FS0

FS1

FS2

FS3

8 PRIMARY FLASH

MEMORY SECTOR SELECTS

FS4

FS5

FS6

FS7

RS0

CSIOP

PSEL0

PSEL1

SRAM SELECT

I/O DECODER

SELECT

PERIPHERAL I/O MODE

SELECT

JTAGSEL

AI05738

33/89

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