PSD4213F1-70UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD4213F1-70UI
STMicroelectronics
PSD4213F1-70UI Datasheet PDF : 89 Pages
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PSD4235G2
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate eight External Chip Se-
lect (ECS0-ECS7), routed to Port C or Port F.
Although External Chip Select (ECS0-ECS7) can
be produced by any Output Macrocell (OMC),
these eight External Chip Select (ECS0-ECS7) on
Port C or Port F do not consume any Output Mac-
rocells (OMC).
As shown in Figure 12, the CPLD has the following
blocks:
s 24 Input Macrocells (IMC)
s 16 Output Macrocells (OMC)
s Product Term Allocator
s AND Array capable of generating up to 196
product terms
s Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
Figure 14. Macrocell and I/O Port
PRODUCT TERMS
FROM OTHER
MACROCELLS
MCU ADDRESS / DATA BUS
CPLD MACROCELLS
PRODUCT TERM
ALLOCATOR
PT PRESET
MCU DATA IN
MCU LOAD
DATA
LOAD
CONTROL
UP TO 10
PRODUCT TERMS
POLARITY
SELECT
PT
CLOCK
GLOBAL
CLOCK
CLOCK
SELECT
PT CLEAR
MACROCELL
OUT TO
MCU
PR DI LD
D/T
Q
D/T/JK FF
SELECT
CK
CL
COMB.
/REG
SELECT
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
I/O PORT INPUT
PT INPUT LATCH GATE/CLOCK
I/O PORTS
LATCHED
ADDRESS OUT
DATA
WR
DQ
CPLD OUTPUT
MUX
I/O PIN
PDR
INPUT
SELECT
DQ
DIR
WR
REG.
INPUT MACROCELLS
QD
ALE/AS
QD
G
AI04945
34/89
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