PSD4245F3V-12UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD4245F3V-12UI
STMicroelectronics
PSD4245F3V-12UI Datasheet PDF : 89 Pages
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PSD4235G2
Table 61. CPLD Combinatorial Timing
Symbol
Parameter
Conditions
-70
Min Max
CPLD Input Pin/
tPD
Feedback to CPLD
20
Combinatorial Output
tEA
CPLD Input to CPLD
Output Enable
21
tER
CPLD Input to CPLD
Output Disable
21
tARP
CPLD Register Clear
or Preset Delay
21
tARPW
CPLD Register Clear
or Preset Pulse Width
10
tARD
CPLD Array Delay
Any
Macrocell
11
Note: 1. Fast Slew Rate output available on Port C and Port F.
-90
Min Max
Fast
PT
Aloc
Turbo Slew
Off rate1
Unit
25 + 2 + 12 – 2 ns
26
+ 12 – 2 ns
26
+ 12 – 2 ns
26
+ 12 – 2 ns
20
+ 12
ns
16 + 2
ns
Table 62. CPLD Macrocell Synchronous Clock Mode Timing
Symbol
Parameter
Conditions
-70
Min Max
-90
Min Max
Maximum Frequency
External Feedback
1/(tS+tCO)
34.4
30.30
fMAX
Maximum Frequency
Internal Feedback
(fCNT)
1/(tS+tCO–10)
Maximum Frequency
Pipelined Data
1/(tCH+tCL)
52.6
83.3
43.48
50.00
tS
Input Setup Time
14
15
tH
Input Hold Time
0
0
tCH
Clock High Time
Clock Input
6
10
tCL
Clock Low Time
Clock Input
6
10
tCO
Clock to Output
Delay
Clock Input
15
18
tARD
CPLD Array Delay Any Macrocell
11
16
Minimum Clock
tMIN
Period 2
tCH+tCL
12
20
Note: 1. Fast Slew Rate output available on Port C and Port F.
2. CLKIN (PD1) tCLCL = tCH + tCL .
Fast
PT
Aloc
Turbo Slew
Off rate1
Unit
MHz
MHz
MHz
+ 2 + 12
ns
ns
ns
ns
– 2 ns
+2
ns
ns
72/89
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