PSD4255F2-15UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD4255F2-15UI
STMicroelectronics
PSD4255F2-15UI Datasheet PDF : 89 Pages
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PSD4235G2
Table 63. CPLD Macrocell Asynchronous Clock Mode Timing
Symbol Parameter
Conditions
-70
Min
Max
-90
Min
Max
Maximum
Frequency
External
Feedback
1/(tSA+tCOA)
38.4
26.32
fMAXA
Maximum
Frequency
Internal
Feedback
(fCNTA)
1/(tSA+tCOA–10)
62.5
35.71
Maximum
Frequency
Pipelined Data
1/(tCHA+tCLA)
47.6
37.03
tSA
Input Setup
Time
6
8
tHA
Input Hold Time
7
12
tCHA
Clock Input
High Time
9
12
tCLA
Clock Input Low
Time
12
15
tCOA
Clock to Output
Delay
21
30
tARDA
CPLD Array
Delay
Any Macrocell
11
16
tMINA
Minimum Clock
Period
1/fCNTA
16
28
PT
Aloc
Turbo Slew
Off Rate
Unit
MHz
MHz
MHz
+ 2 + 12
ns
ns
+ 12
ns
+ 12
ns
+ 12 – 2 ns
+2
ns
ns
73/89
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