TDA75610SLV-ZSX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
TDA75610SLV-ZSX
STMicroelectronics
TDA75610SLV-ZSX Datasheet PDF : 42 Pages
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I2C bus
TDA75610SLV
9.3.2
9.3.3
9.3.4
Start and stop conditions
As shown by Figure 40 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH.
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
Acknowledge
The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 41). The receiver** has to pull-down (LOW) the SDA line during the
acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse.
* Transmitter
– master µP) when it writes an address to the TDA75610SLV
– slave (TDA75610SLV) when the µP reads a data byte from TDA75610SLV
** Receiver
– slave (TDA75610SLV) when the µP writes an address to the TDA75610SLV
– master (µP) when it reads a data byte from TDA75610SLV
Figure 39. Data validity on the I2C bus
3$!
3#,
$!4! ,).%
34!",% $!4!
6!,)$
#(!.'%
$!4!
!,,/7%$
Figure 40. Timing diagram on the I2C bus
'!0'03
3#,
3$!
)#"53
34!24
34/0
Figure 41. Acknowledge on the I2C bus
'!0'03
3#,
3$!
34!24
-3"
!#+./7,%$'-%.4
&2/- 2%#%)6%2
'!0'03
30/42
DocID025599 Rev 6
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