PIC18F46K80T-I/SP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F46K80T-I/SP
Microchip Technology
PIC18F46K80T-I/SP Datasheet PDF : 623 Pages
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PIC18F66K80 FAMILY
REGISTER 11-1: PADCFG1: PAD CONFIGURATION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
RDPU(1)
REPU(1)
RFPU(2)
RGPU(2)
—
—
bit 7
U-0
R/W-0
—
CTMUDS
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-1
bit 0
RDPU: PORTD Pull-up Enable bit(1)
1 = PORTD pull-up resistors are enabled by individual port latch values
0 = All PORTD pull-up resistors are disabled
REPU: PORTE Pull-up Enable bit(1)
1 = PORTE pull-up resistors are enabled by individual port latch values
0 = All PORTE pull-up resistors are disabled
RFPU: PORTF Pull-up Enable bit(2)
1 = PORTF pull-up resistors are enabled by individual port latch values
0 = All PORTF pull-up resistors are disabled
RGPU: PORTG Pull-up Enable bit(2)
1 = PORTG pull-up resistors are enabled by individual port latch values
0 = All PORTG pull-up resistors are disabled
Unimplemented: Read as ‘0’
CTMUDS: CTMU Comparator Data Select bit
1 = External comparator (with output on pin CTDIN) is used for CTMU compares
0 = Internal comparator (CMP2) is used for CTMU compares
Note 1: These bits are unimplemented on 28-pin devices.
2: These bits are unimplemented on 40-pin devices.
REGISTER 11-2: WPUB: WEAK PULL-UP PORTB ENABLE REGISTER
R/W-x
WPUB7
bit 7
R/W-x
WPUB6
R/W-x
WPUB5
R/W-x
WPUB4
R/W-x
WPUB3
R/W-x
WPUB2
R/W-x
WPUB1
R/W-x
WPUB0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
WPUB<7:0>: Weak Pull-Up Enable Register bits
1 = Pull-up is enabled on corresponding PORTB pin when RBPU = 0 and the pin is an input
0 = Pull-up is disabled on corresponding PORTB pin
DS39977F-page 172
2010-2012 Microchip Technology Inc.
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