PIC18F46K80T-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F46K80T-I/SP

28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

Microchip Technology 

PIC18F66K80 FAMILY

TABLE 11-9: PORTE FUNCTIONS (CONTINUED)

Pin Name

Function

TRIS

Setting

I/O I/O Type

Description

RE5/CANTX

RE5(1)

0

1

CANTX(1,2)

0

RE6/RX2/DT2

RE6(1)

0

1

RX2(1)

1

DT2(1)

1

O

DIG LATE<5> data output.

I

ST PORTE<5> data input.

O

DIG CAN bus TX.

O

DIG LATE<6> data output.

I

ST PORTE<6> data input.

I

ST Asynchronous serial receive data input (EUSARTx module).

O

DIG Synchronous serial data output (EUSARTx module); takes priority over

port data.

RE7/TX2/CK2

RE7(1)

TX2(1)

CK2(1)

1

I

ST Synchronous serial data input (EUSARTx module); user must

configure as an input.

0

O

DIG LATE<7> data output.

1

I

ST PORTE<7> data input.

0

O

DIG Asynchronous serial data output (EUSARTx module); takes priority

over port data.

0

O

DIG Synchronous serial clock output (EUSARTx module); user must

configure as an input.

1

I

ST Synchronous serial clock input (EUSARTx module); user must config-

ure as an input.

Legend:

Note 1:

2:

O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)

These bits are unavailable for 40 and 44-pin devices (PIC18F4XK0).

This is the alternate pin assignment for CANRX and CANTX on 64-pin devices (PIC18F6XK80) when the CANMX

Configuration bit is cleared.

TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

PORTE

RE7(1)

RE6(1)

RE5(1)

RE4(1)

RE3

LATE

LATE7

LATE6

LATE5 LATE4

—

TRISE

TRISE7

TRISE6 TRISE5 TRISE4

—

PADCFG1

RDPU

REPU

RFPU(1) RGPU(1)

—

ANCON0

ANSEL7

ANSEL6 ANSEL5 ANSEL4 ANSEL3

Legend: Shaded cells are not used by PORTE.

Note 1: These bits are unimplemented on 44-pin devices, read as ‘0’.

RE2

LATE2

TRISE2

—

ANSEL2

Bit 1

RE1

LATE1

TRISE1

—

ANSEL1

Bit 0

RE0

LATE0

TRISE0

CTMUDS

ANSEL0

DS39977F-page 188

 2010-2012 Microchip Technology Inc.

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