PIC18F46K80T-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F46K80T-I/SP

28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

Microchip Technology 

PIC18F66K80 FAMILY

FIGURE 14-1:

TIMER1 BLOCK DIAGRAM

T1GSS<1:0>

T1G

00

T1GSPM

From TMR2

01

Match PR2

From Comparator 1

Output

10

From Comparator 2

Output

11

T1GPOL

T1G_IN

TMR1ON

T1GTM

DQ

CK Q

R

Set Flag bit,

TMR1IF, on

Overflow

TMR1(2)

TMR1H

TMR1L

0

Single Pulse

1

Acq. Control

T1GGO/T1DONE

0

T1GVAL D Q

1

Q1 EN

Interrupt

det

TMR1ON

TMR1GE

Data Bus

RD

T1GCON

Set

TMR1GIF

EN

T1CLK

0

QD

Synchronized

Clock Input

1

SOSCO/SCLKI

OUT(4)

TMR1CS<1:0>

T1SYNC

SOSCI

T1CON.SOSCEN

T3CON.SOSCEN

SOSCGO

SCS<1:0> = 01

T1CKI

SOSC

EN

(1)

10

Prescaler

Synchronize(3)

1

1, 2, 4, 8

det

0

FOSC

Internal 01

2

Clock

T1CKPS<1:0>

FOSC/4

Internal 00

Clock

FOSC/2

Internal

Clock

Sleep Input

Note 1:

2:

3:

4:

ST Buffer is high-speed type when using T1CKI.

Timer1 register increments on rising edge.

Synchronize does not operate while in Sleep.

The output of SOSC is determined by the SOSCSEL<1:0> Configuration bits.

 2010-2012 Microchip Technology Inc.

DS39977F-page 213

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