PIC18F65K80T-I/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F65K80T-I/SS

28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

Microchip Technology 

PIC18F66K80 FAMILY

GOTO

Unconditional Branch

Syntax:

GOTO k

Operands:

Operation:

Status Affected:

0  k  1048575

k  PC<20:1>

None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

Description:

1110 1111 k7kkk kkkk0

1111 k19kkk kkkk kkkk8

GOTO allows an unconditional branch

anywhere within entire 2-Mbyte memory

range. The 20-bit value ‘k’ is loaded into

PC<20:1>. GOTO is always a two-cycle

instruction.

Words:

2

Cycles:

Q Cycle Activity:

Q1

Decode

2

Q2

Read literal

‘k’<7:0>,

No

operation

No

operation

Q3

No

operation

No

operation

Q4

Read literal

‘k’<19:8>,

Write to PC

No

operation

Example:

GOTO THERE

After Instruction

PC = Address (THERE)

INCF

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

Increment f

INCF f {,d {,a}}

0  f  255

d  [0,1]

a  [0,1]

(f) + 1  dest

C, DC, N, OV, Z

0010 10da ffff ffff

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 29.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

1

1

Q2

Read

register ‘f’

Q3

Process

Data

Q4

Write to

destination

Example:

INCF

Before Instruction

CNT

Z

C

DC

= FFh

=0

=?

=?

After Instruction

CNT

Z

C

DC

= 00h

=1

=1

=1

CNT, 1, 0

DS39977F-page 504

 2010-2012 Microchip Technology Inc.

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