PIC18F45K80T-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F45K80T-I/SO

28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

Microchip Technology 

PIC18F66K80 FAMILY

LFSR

Load FSR

Syntax:

LFSR f, k

Operands:

Operation:

Status Affected:

0f2

0  k  4095

k  FSRf

None

Encoding:

Description:

1110

1111

1110 00ff k11kkk

0000 k7kkk kkkk

The 12-bit literal ‘k’ is loaded into the

file select register pointed to by ‘f’.

Words:

2

Cycles:

Q Cycle Activity:

Q1

Decode

2

Q2

Read literal

‘k’ MSB

Decode

Read literal

‘k’ LSB

Q3

Process

Data

Process

Data

Q4

Write

literal ‘k’

MSB to

FSRfH

Write literal

‘k’ to FSRfL

Example:

LFSR 2, 3ABh

After Instruction

FSR2H

FSR2L

= 03h

= ABh

MOVF

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

Move f

MOVF f {,d {,a}}

0  f  255

d  [0,1]

a  [0,1]

f  dest

N, Z

0101 00da ffff ffff

The contents of register ‘f’ are moved to

a destination dependent upon the

status of ‘d’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

Location ‘f’ can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 29.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

1

1

Q2

Read

register ‘f’

Q3

Process

Data

Q4

Write

W

Example:

MOVF

Before Instruction

REG

=

W

=

After Instruction

REG

=

W

=

REG, 0, 0

22h

FFh

22h

22h

 2010-2012 Microchip Technology Inc.

DS39977F-page 507

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