PIC18F65K80T-I/SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F65K80T-I/SS
Microchip Technology
PIC18F65K80T-I/SS Datasheet PDF : 623 Pages
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PIC18F66K80 FAMILY
FIGURE 31-14:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
70
SCK
(CKPx = 0)
71
72
SCK
(CKPx = 1)
80
SDO
MSb
bit 6 - - - - - - 1
75, 76
SDI
MSb In
bit 6 - - - - 1
74
Note: Refer to Figure 31-3 for load conditions.
LSb
LSb In
83
77
TABLE 31-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70 TSSL2SCH, SS to SCK or SCK Input
TSSL2SCL
3 TCY
—
70A TSSL2WB SS to write to SSPBUF
3 TCY
—
71
TSCH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TSCL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
40
—
75
TDOR
SDO Data Output Rise Time
—
25
76
TDOF
SDO Data Output Fall Time
—
25
77 TSSH2DOZ SS to SDO Output High-Impedance
10
50
78
TSCR
SCK Output Rise Time (Master mode)
—
25
79
TSCF
SCK Output Fall Time (Master mode)
—
25
80 TSCH2DOV, SDO Data Output Valid after SCK Edge
TSCL2DOV
—
50
82 TSSL2DOV SDO Data Output Valid after SS Edge
—
50
83 TSCH2SSH, SS after SCK Edge
TSCL2SSH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter 73A.
2: Only if Parameter 71A and 72A are used.
ns
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
2010-2012 Microchip Technology Inc.
DS39977F-page 573
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