PIC18F46K80T-E/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F46K80T-E/SS

28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

Microchip Technology 

PIC18F66K80 FAMILY

FIGURE 31-21: A/D CONVERSION TIMING

BSF ADCON0, GO

(Note 2)

131

Q4

130

A/D CLK

132

A/D DATA

11

10

9 ... ... 2

1

0

ADRES

ADIF

GO

SAMPLE

OLD_DATA

SAMPLING STOPPED

NEW_DATA

TCY (Note 1)

DONE

Note 1:

2:

If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to

be executed.

This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

TABLE 31-26: A/D CONVERSION REQUIREMENTS

Param

No.

Symbol

Characteristic

Min Max Units

Conditions

130 TAD

A/D Clock Period

0.8 12.5(1) s TOSC based, VREF  3.0V

1.4

25(1)

s VDD = 3.0V; TOSC based,

VREF full range

—

1

s A/D RC mode

—

3

s VDD = 3.0V; A/D RC mode

131 TCNV Conversion Time

(not including acquisition time)(2)

14

15

TAD

132 TACQ Acquisition Time(3)

1.4

—

s -40°C to +125°C

135 TSWC Switching Time from Convert  Sample

— (Note 4)

TBD TDIS Discharge Time

0.2

—

s -40°C to +125°C

Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

2: ADRES registers may be read on the following TCY cycle.

3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale

after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.

4: On the following cycle of the device clock.

DS39977F-page 580

 2010-2012 Microchip Technology Inc.

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