ST7263
Figure 11. Low Voltage Detector functional Diagram
Figure 12. Low Voltage Reset Signal Output
RESET
VDD
LOW VOLTAGE
DETECTOR
VIT+
VIT-
INTERNAL
RESET
VDD
FROM
WATCHDOG
RESET
RESET
Note: Hysteresis (VIT+-VIT-) = Vhys
Figure 13. Temporization timing diagram after an internal Reset
VIT+
VDD
Addresses
temporization (4096 CPU clock cycles)
$FFFE
Figure 14. Reset Timing Diagram
VDD
tDDR
OSCIN
fCPU
tOXOV
PC
RESET
WATCHDOG RESET
FFFE FFFF
4096 CPU
CLOCK
CYCLES
DELAY
Note: Refer to Electrical Characteristics for values of tDDR, tOXOV, VIT+, VIT- and Vhys
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