ST7263
5.3 WATCHDOG TIMER (WDG)
5.3.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
Figure 22. Watchdog Block Diagram
5.3.2 Main Features
s Programmable timer (64 increments of 49152
CPU cycles)
s Programmable reset
s Reset (if watchdog activated) when the T6 bit
reaches zero
RESET
WDGA T6
WATCHDOG CONTROL REGISTER (CR)
T5 T4 T3 T2 T1 T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER
÷49152
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