ST72T631K4D0 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72T631K4D0

LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C

STMicroelectronics 

ST7263

5.7 I²C BUS INTERFACE (I²C)

5.7.1 Introduction

The I²C Bus Interface serves as an interface be-

tween the microcontroller and the serial I²C bus. It

provides both multimaster and slave functions,

and controls all I²C bus-specific sequencing, pro-

tocol, arbitration and timing. It supports fast I²C

mode (400 kHz).

5.7.2 Main Features

s Parallel-bus/I²C protocol converter

s Multi-master capability

s 7-bit Addressing

s Transmitter/Receiver flag

s End-of-byte transmission flag

s Transfer problem detection

I²C Master Features:

s Clock generation

s I²C bus busy flag

s Arbitration Lost Flag

s End of byte transmission flag

s Transmitter/Receiver Flag

s Start bit detection flag

s Start and Stop generation

I²C Slave Features:

s Stop bit detection

s I²C bus busy flag

s Detection of misplaced start or stop condition

s Programmable I²C Address detection

s Transfer problem detection

s End-of-byte transmission flag

s Transmitter/Receiver flag

5.7.3 General Description

In addition to receiving and transmitting data, this

interface converts it from serial to parallel format

and vice versa, using either an interrupt or polled

Figure 38. I²C BUS Protocol

SDA

MSB

handshake. The interrupts are enabled or disabled

by software. The interface is connected to the I²C

bus by a data pin (SDAI) and by a clock pin (SCLI).

It can be connected both with a standard I²C bus

and a Fast I²C bus. This selection is made by soft-

ware.

Mode Selection

The interface can operate in the four following

modes:

– Slave transmitter/receiver

– Master transmitter/receiver

By default, it operates in slave mode.

The interface automatically switches from slave to

master after it generates a START condition and

from master to slave in case of arbitration loss or a

STOP generation, this allows Multi-Master capa-

bility.

Communication Flow

In Master mode, it initiates a data transfer and

generates the clock signal. A serial data transfer

always begins with a start condition and ends with

a stop condition. Both start and stop conditions are

generated in master mode by software.

In Slave mode, the interface is capable of recog-

nising its own address (7-bit), and the General Call

address. The General Call address detection may

be enabled or disabled by software.

Data and addresses are transferred as 8-bit bytes,

MSB first. The first byte following the start condi-

tion is the address byte; it is always transmitted in

Master mode.

A 9th clock pulse follows the 8 clock cycles of a

byte transfer, during which the receiver must send

an acknowledge bit to the transmitter. Refer to Fig-

ure 1.

ACK

SCL

1

2

8

9

START

CONDITION

STOP

CONDITION

VR02119B

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