ST7263
7.6 LOW VOLTAGE DETECTOR (LVD) CHARACTERISTICS
LOW VOLTAGE RESET Electrical Specifications
Symbol
Parameter
Conditions
VIT+
VIT-
Vhys
Low Voltage Reset Threshold
VDD rising
Low Voltage Reset Threshold
VDD falling
Hysteresis (VIT+ - VIT-)
VDD Max. Variation
50mV/µs
VDD Max. Variation
50mV/µs
Min
Typ
Max
Unit
3.6
3.75
4.0
V
3.2
3.5
3.7
V
200
250
mV
7.7 CONTROL TIMING CHARACTERISTICS
(Operating conditions TA = 0 to +70°C unless otherwise specified)
CONTROL TIMINGS
Symbol
Parameter
fOSC
fCPU
tRL
tPORL
TDOGL
Oscillator Frequency
Operating Frequency
External RESET
Input pulse Width
Internal Power Reset Duration
Watchdog & Low Voltage Reset
Output Pulse Width
tDOG
tOXOV
tDDR
Watchdog Time-out
Crystal Oscillator
Start-up Time
Power up rise time
Conditions
fcpu = 8MHz
from VDD = 0 to 4V
Min
1.5
4096
200
49152
6
Value
Typ.
Max
24
8
3145728
384
50
100
Unit
MHz
MHz
tCPU
tCPU
ns
tCPU
ms
ms
ms
Note 1: The minimum period tILIL should not be less than the number of cycle times it takes to execute the
interrupt service routine plus 21 cycles.
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