ST7262
Table 2. Hardware Register Map
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
Block
Port A
Port B
Port C
Port D
ADC
WDG
SPI
PWM ART
SCI
Register
Label
Register Name
PADR
PADDR
Port A Data Register
Port A Data Direction Register
PBDR
PBDDR
Port B Data Register
Port B Data Direction Register
PCDR
PCDDR
Port C Data Register
Port C Data Direction Register
PDDR
PDDDR
Port D Data Register
Port D Data Direction Register
ITRFRE1 Interrupt Register 1
MISC
Miscellaneous Register
ADCDRMSB ADC Data Register (bit 9:2)
ADCDRLSB ADC Data Register (bit 1:0)
ADCCSR ADC Control Status Register
WDGCR
Watchdog Control Register
Reset
Status
00h1)
00h
00h1)
00h
00h1)
00h
00h1)
00h
00h
00h
00h
00h
00h
7Fh
Remarks
R/W2)
R/W2)
R/W2)
R/W2)
R/W2)
R/W2)
R/W2)
R/W2)
R/W
R/W
Read Only
Read Only
R/W
R/W
Reserved Area (3 Bytes)
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control Status Register
xxh
R/W
0xh
R/W
00h
Read Only
PWMDCR1 PWM AR Timer Duty Cycle Register 1
00h
R/W
PWMDCR0 PWM AR Timer Duty Cycle Register 0
00h
R/W
PWMCR
PWM AR Timer Control Register
00h
R/W
ARTCSR Auto-Reload Timer Control/Status Register
00h
R/W
ARTCAR Auto-Reload Timer Counter Access Register
00h
R/W
ARTARR Auto-Reload Timer Auto-Reload Register
00h
R/W
ARTICCSR ART Input Capture Control/Status Register
00h
R/W
ARTICR1 ART Input Capture Register 1
00h
Read Only
ARTICR2 ART Input Capture Register 2
00h
Read Only
SCIERPR
SCIETPR
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCI Extended Receive Prescaler register
SCI Extended Transmit Prescaler Register
Reserved Area
SCI Status register
SCI Data register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
00h
R/W
00h
R/W
--
C0h Read Only
xxh
R/W
00h
R/W
x000 0000b R/W
00h
R/W
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