ST72622L2M1L View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72622L2M1L
STMicroelectronics
ST72622L2M1L Datasheet PDF : 133 Pages
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ST7262
Pin n°
Pin Name
18 22 9
8
14
19
PB6/PWM0/IT7/
ICCDATA
19 23 10
9
15
20
PB5/ARTIC2/IT6/
ICCCLK
20 24 11 10 16 1 PB4/ARTIC1/IT5
21 25 12 11 17 2 PB3/ARTCLK
22 26 13 12 18 3 PB2/TDO
23 27 14 13 19 4 PB1/RDI
24 28 15 14 20 5 PB0/MCO
25 29 16 15 - - PA7/AIN7
26 30 17 16 - - PA6/AIN6
27 31 18 17 - - PA5/AIN5
28 32 19 18 - - PA4/AIN4
29 33 20 19 - - PA3/AIN3/IT4
30 34 21 20 1 6 PA2/AIN2/IT3
31 35 22 21 2 7 PA1/AIN1/IT2
32 36 23 22 3
8
PA0/AIN0/IT1/
USBOE
33 37 30 29 10 15 RESET
34 38 24 23 - - VSSA
35 39 25 24 5 10 USBDM
36 40 26 25 6 11 USBDP
37 41 27 26 7 12 USBVCC
38 42 28 27 - - VDDA
39 - - - - - Reserved
40 1 - - - - PD6
41 2 - - - - PD5
42 3 - - - - PD4
Level
Port / Control
Main
Input
Output
Function
(after
Alternate Function
reset)
I/O CT HS x
\
I/O CT HS x
I/O CT HS x
I/O CT HS x
I/O CT HS x
I/O CT HS x
I/O CT HS x
I/O CT
x
I/O CT
x
I/O CT
x
I/O CT
x
I/O CT
x
I/O CT
x
I/O CT
x
I/O CT
x
I/O C
S
I/O
I/O
S
S
/
/
x
x
x
x
\x
\x
\x
\x
I/O CT
x
I/O CT
x
I/O CT
x
x Port B6
x Port B5
x Port B4
x Port B3
x Port B2
x Port B1
x Port B0
ART PWM output 0/
Interrupt 7 input/In-
Circuit Communica-
tion Data
ART Input Capture 2/
Interrupt 6 input/
In-Circuit Communi-
cation Clock
ART Input Capture
1/Interrupt 5 input
ART Clock input
SCI Transmit Data
Output 1)
SCI Receive Data
Input 1)
CPU clock output
x Port A7 ADC Analog Input 7
x Port A6 ADC Analog Input 6
x Port A5 ADC Analog Input 5
x Port A4 ADC Analog Input 4
x Port A3
ADC Analog Input 3/
Interrupt 4 input
x Port A2
ADC Analog Input 2/
Interrupt 3 input
x Port A1
ADC Analog Input 1/
Interrupt 2 input
x Port A0
ADC Analog Input 0/
Interrupt 1 input/
USB Output Enable
Top priority non maskable inter-
rupt (active low)
Analog Ground Voltage, must
be connected externally to VSS.
USB bidirectional data (data -)
USB bidirectional data (data +)
USB power supply 3.3V output
Analog Power Supply Voltage,
must be connected externally to
VDD.
Must be left unconnected.
x Port D6
x Port D5
x Port D4
9/132
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