ST72P623 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72P623
STMicroelectronics
ST72P623 Datasheet PDF : 139 Pages
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ST7262xxx
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.5 Error Flags
10.4.5.2 Overrun Condition (OVR)
10.4.5.1 Master Mode Fault (MODF)
An overrun condition occurs, when the master de-
Master mode fault occurs when the master device
has its SS pin pulled low.
vice has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
When a Master mode fault occurs:
When an Overrun occurs:
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set.
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph- In this case, the receiver buffer contains the byte
eral.
) – The MSTR bit is reset, thus forcing the device
t(s into slave mode.
c Clearing the MODF bit is done through a software
u sequence:
d 1. A read access to the SPICSR register while the
ro MODF bit is set.
P 2. A write to the SPICR register.
te Notes: To avoid any conflicts in an application
le with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
so SPE and MSTR bits may be restored to their orig-
b inal state during or after this clearing sequence.
O Hardware does not allow the user to set the SPE
- and MSTR bits while the MODF bit is set except in
) the MODF bit clearing sequence.
t(s In a slave device, the MODF bit can not be set, but
c in a multimaster configuration the device can be in
u slave mode with the MODF bit set.
d The MODF bit indicates that there might have
ro been a multimaster conflict and allows software to
P handle this using an interrupt routine and either
perform to a reset or return to an application de-
te fault state.
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
The OVR bit is cleared by reading the SPICSR
register.
10.4.5.3 Write Collision Error (WCOL)
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode. See also Section 10.4.3.2 Slave Select
Management.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 44).
le Figure 44. Clearing the WCOL bit (Write Collision Flag) Software Sequence
so Clearing sequence after SPIF = 1 (end of a data byte transfer)
Ob Read SPICSR
1st Step
RESULT
2nd Step
Read SPIDR
SPIF =0
WCOL=0
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
2nd Step
Read SPICSR
Read SPIDR
RESULT
WCOL=0
Note: Writing to the SPIDR regis-
ter instead of reading it does not
reset the WCOL bit
Doc ID 6996 Rev 5
61/139
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