ST7262xxx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIERPR)
REGISTER (SCIETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi- Allows setting of the External Prescaler rate divi-
sion factor for the receive circuit.
sion factor for the transmit circuit.
7
0
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
t(s) Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register.
c The extended Baud Rate Generator is activated
u when a value different from 00h is stored in this
d register. Therefore the clock frequency issued
ro from the 16 divider (see Figure 48) is divided by
P the binary factor set in the SCIERPR register (in
the range 1 to 255).
te The extended baud rate generator is not used af-
le ter a reset.
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 48) is divided by
the binary factor set in the SCIETPR register (in
the range 1 to 255).
The extended baud rate generator is not used af-
ter a reset.
so Table 21. Baudrate Selection
) - Ob Symbol
Parameter
fCPU
Conditions
Accuracy vs
Standard
Prescaler
t(s Conventional Mode
c TR (or RR)=128, PR=13
u TR (or RR)= 32, PR=13
d TR (or RR)= 16, PR=13
ro ~0.16% TR (or RR)= 8, PR=13
P fTx
Communication frequency 8 MHz
te fRx
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 3
TR (or RR)= 2, PR=13
le TR (or RR)= 1, PR=13
Obso ~0.79%
Extended Mode
ETPR (or ERPR) = 35,
TR (or RR)= 1, PR=1
Standard
Baud
Rate
Unit
300 ~300.48
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69
9600 ~9615.38
10400 ~10416.67 Hz
19200 ~19230.77
38400 ~38461.54
14400 ~14285.71
Doc ID 6996 Rev 5
81/139