PIC18F85J50-I/PT View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F85J50-I/PT

64/80-Pin High-Performance, 1-Mbit Flash USB Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC18F87J50 FAMILY

TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin Buffer

80-TQFP Type Type

Description

PORTD is a bidirectional I/O port (continued).

RD6/AD6/PMD6/

SCK2/SCL2

RD6

AD6

PMD6(6)

SCK2

SCL2

64

I/O ST

I/O TTL

I/O TTL

I/O ST

I/O ST

Digital I/O.

External memory address/data 6.

Parallel Master Port data.

Synchronous serial clock input/output for SPI mode.

Synchronous serial clock input/output for I2C™ mode.

RD7/AD7/PMD7/SS2

RD7

AD7

PMD7(6)

SS2

63

I/O ST

Digital I/O.

I/O TTL

External memory address/data 7.

I/O TTL

Parallel Master Port data.

I

TTL

SPI slave select input.

Legend:

Note 1:

2:

3:

4:

5:

6:

7:

8:

TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

Analog = Analog input

I = Input

O

= Output

P = Power

OD

= Open-Drain (no P diode to VDD)

Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller

mode).

Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).

Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).

Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).

Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).

Pin placement when PMPMX = 1.

Pin placement when PMPMX = 0.

RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

© 2007 Microchip Technology Inc.

Preliminary

DS39775B-page 25

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