S25FL128SAGNHIE01 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL128SAGNHIE01
Cypress Semiconductor
S25FL128SAGNHIE01 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
9.5.3
Quad Page Program (QPP 32h or 38h, or 4QPP 34h)
The Quad-input Page Program (QPP) command allows bytes to be programmed in the memory (changing bits from 1 to 0). The
Quad-input Page Program (QPP) command allows up to a page size (either 256 or 512 bytes) of data to be loaded into the Page
Buffer using four signals: IO0-IO3. QPP can improve performance for PROM Programmer and applications that have slower clock
speeds (< 12 MHz) by loading 4 bits of data per clock cycle. Systems with faster clock speeds do not realize as much benefit for the
QPP command since the inherent page program time becomes greater than the time it takes to clock-in the data. The maximum
frequency for the QPP command is 80 MHz.
To use Quad Page Program the Quad Enable Bit in the Configuration Register must be set (QUAD=1). A Write Enable command
must be executed before the device will accept the QPP command (Status
Register 1, WEL=1).
The instruction
32h (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
32h (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
38h (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
38h (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
34h is followed by a 4-byte address (A31-A0)
and at least one data byte, into the IO signals. Data must be programmed at previously erased (FFh) memory locations.
QPP requires programming to be done one full page at a time. While less than a full page of data may be loaded for programming,
the entire page is considered programmed, any locations not filled with data will be left as ones, the same page must not be
programmed more than once.
All other functions of QPP are identical to Page Program. The QPP command sequence is shown in Figure 9.55.
Figure 9.55 Quad 512-Byte Page Program Command Sequence (3-Byte Address, 32h or 38h)
CS#
SCK
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
Instruction
24-Bit
Address
IO0
23 22 21
3 210 40 40 40 40
IO1
*
5 1 5 1 56 1 5 1
IO2
62626262
IO3
73737373
B*yte 1 B*yte 2 B*yte 3 B*yte 4
CS#
SCK
IO0
IO1
IO2
IO3
*MSB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
40 40 40 40 40 40 40 40 40 40 40 40
5151515151515151 51515151
6262626262626262 62626262
73
*
Byte 5
73
*
Byte 6
73
*
Byte 7
73
*
Byte 8
7 3 7 3 7 37 3
*** *
Byte 9 Byte 10 Byte 11 Byte 12
7 37 3 7 37 3
*** *
Byte 509 Byte 510Byte 511 Byte 512
Document Number: 001-98283 Rev. *I
Page 100 of 144
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