S25FL128SDSMHND10 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL128SDSMHND10

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

9.8 Advanced Sector Protection Commands

9.8.1

ASP Read (ASPRD 2Bh)

The ASP Read instruction 2Bh is shifted into SI by the rising edge of the SCK signal. Then the 16-bit ASP register contents is shifted

out on the serial output SO, least significant byte first. Each bit is shifted out at the SCK frequency by the falling edge of the SCK

signal. It is possible to read the ASP register continuously by providing multiples of 16 clock cycles. The maximum operating clock

frequency for the ASP Read (ASPRD) command is 133 MHz.

Figure 9.70 ASPRD Command

CS#

SCK

SI

SO

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Instruction

7 65 43 21 0

MSB

High Impedance

Register Out

Register Out

7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7

MSB

MSB

MSB

9.8.2

ASP Program (ASPP 2Fh)

Before the ASP Program (ASPP) command can be accepted by the device, a Write Enable (WREN) command must be issued. After

the Write Enable (WREN) command has been decoded, the device will set the Write Enable Latch (WEL) in the Status Register to

enable any write operations.

The ASPP command is entered by driving CS# to the logic low state, followed by the instruction and two data bytes on SI, least

significant byte first. The ASP Register is two data bytes in length.

The ASPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner as any other

programming operation.

CS# input must be driven to the logic high state after the sixteenth bit of data has been latched in. If not, the ASPP command is not

executed. As soon as CS# is driven to the logic high state, the self-timed ASPP operation is initiated. While the ASPP operation is in

progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a

1 during the self-timed ASPP operation, and is a 0 when it is completed. When the ASPP operation is completed, the Write Enable

Latch (WEL) is set to a 0.

Figure 9.71 ASPP Command

CS#

SCK

SI

SO

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Instruction

Register In

76

MSB

54321

High Impedance

07 6 5

MSB

432

1 0 15 14 13 12 11 10 9 8

Document Number: 001-98283 Rev. *I

Page 110 of 144

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