S25FL128SAGNFNQ01 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL128SAGNFNQ01
Cypress Semiconductor
S25FL128SAGNFNQ01 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
9.8.7
PPB Erase (PPBE E4h)
The PPB Erase (PPBE) command sets all PPB bits to 1. Before the PPB Erase command can be accepted by the device, a Write
Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status
Register to enable any write operations.
The instruction E4h is shifted into SI by the rising edges of the SCK signal.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. This will initiate the
beginning of internal erase cycle, which involves the pre-programming and erase of the entire PPB memory array. Without CS#
being driven to the logic high state after the eighth bit of the instruction, the PPB erase operation will not be executed.
With the internal erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to check if the operation has
been completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been completed.
Erase suspend is not allowed during PPB Erase.
Figure 9.76 PPB Erase Command Sequence
CS#
SCK
SI
SO
0 12 3 4 5 6 7
Instruction
76543210
MSB
High Impedance
9.8.8
PPB Lock Bit Read (PLBRD A7h)
The PPB Lock Bit Read (PLBRD) command allows the PPB Lock Register contents to be read out of SO. It is possible to read the
PPB lock register continuously by providing multiples of eight clock cycles. The PPB Lock Register contents may only be read when
the device is in standby state with no other operation in progress. It is recommended to check the Write-In Progress (WIP) bit of the
Status Register before issuing a new command to the device.
CS#
SCK
SI
SO
Phase
Figure 9.77 PPB Lock Register Read Command Sequence
76543210
7 6 5 43 2 1 0 7 6 5 4 3 2 1 0
Instruction
Register Read
Repeat Register Read
9.8.9
PPB Lock Bit Write (PLBWR A6h)
The PPB Lock Bit Write (PLBWR) command clears the PPB Lock Register to zero. Before the PLBWR command can be accepted
by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch
(WEL) in the Status Register to enable any write operations.
The PLBWR command is entered by driving CS# to the logic low state, followed by the instruction.
CS# must be driven to the logic high state after the eighth bit of instruction has been latched in. If not, the PLBWR command is not
executed. As soon as CS# is driven to the logic high state, the self-timed PLBWR operation is initiated. While the PLBWR operation
is in progress, the Status Register may still be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress
Document Number: 001-98283 Rev. *I
Page 113 of 144
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