S25FL256SDPMFV711 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDPMFV711

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

(WIP) bit is a 1 during the self-timed PLBWR operation, and is a 0 when it is completed. When the PLBWR operation is completed,

the Write Enable Latch (WEL) is set to a 0. The maximum clock frequency for the PLBWR command is 133 MHz.

Figure 9.78 PPB Lock Bit Write Command Sequence

CS#

SCK

SI

SO

0 12 3 4 5 6 7

Instruction

76543210

MSB

High Impedance

9.8.10

Password Read (PASSRD E7h)

The correct password value may be read only after it is programmed and before the Password Mode has been selected by

programming the Password Protection Mode bit to 0 in the ASP Register (ASP[2]). After the Password Protection Mode is selected

the PASSRD command is ignored.

The PASSRD command is shifted into SI. Then the 64-bit Password is shifted out on the serial output SO, least significant byte first,

most significant bit of each byte first. Each bit is shifted out at the SCK frequency by the falling edge of the SCK signal. It is possible

to read the Password continuously by providing multiples of 64 clock cycles. The maximum operating clock frequency for the

PASSRD command is 133 MHz.

Figure 9.79 Password Read Command Sequence

CS#

SCK

0 1 2 3 4 5 6 7 8 9 10 11

69 70 71 72

Instruction

SI

76543210

MSB

Password Least Sig. Byte First

SO

High Impedance

7654

58 57 56 7

MSB

MSB

9.8.11

Password Program (PASSP E8h)

Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN) command must be

issued and decoded by the device. After the Write Enable (WREN) command has been decoded, the device sets the Write Enable

Latch (WEL) to enable the PASSP operation.

The password can only be programmed before the Password Mode is selected by programming the Password Protection Mode bit

to 0 in the ASP Register (ASP[2]). After the Password Protection Mode is selected the PASSP command is ignored.

The PASSP command is entered by driving CS# to the logic low state, followed by the instruction and the password data bytes on

SI, least significant byte first, most significant bit of each byte first. The password is sixty-four (64) bits in length.

CS# must be driven to the logic high state after the sixty-fourth (64th) bit of data has been latched. If not, the PASSP command is not

executed. As soon as CS# is driven to the logic high state, the self-timed PASSP operation is initiated. While the PASSP operation

is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit

is a 1 during the self-timed PASSP cycle, and is a 0 when it is completed. The PASSP command can report a program error in the

P_ERR bit of the status register. When the PASSP operation is completed, the Write Enable Latch (WEL) is set to a 0. The

maximum clock frequency for the PASSP command is 133 MHz.

Document Number: 001-98283 Rev. *I

Page 114 of 144

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