S25FL128SDSMFVC03 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL128SDSMFVC03

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

13. Revision History

Spansion Publication Number: S25FL128S_256S_00

Section

Description

Revision 01 (May 25, 2011)

Initial release

Revision 02 (November 18, 2011)

Global

Promoted data sheet to Preliminary status

Corrected minor typos and grammatical errors

Performance Summary

Updated the Serial Read 50 MHz current consumption value from 14 mA (max) to 16 mA (max)

Updated the Serial Read 133 MHz current consumption value from 25 mA (max) to 33 mA (max)

Power-Up and Power-Down

DC Characteristics

Removed the statement “The device draws ICC1 (50 MHz value) during tPU”

Updated the ICC1 Active Power Supply Current (READ) Serial SDR @ 50 MHz maximum value from 14

mA to 16 mA

Updated the ICC1 Active Power Supply Current (READ) Serial SDR @ 133 MHz maximum value from 25

mA to 33 mA

SDR AC Characteristics

Added the tCSH CS# Active Hold Time (Relative to SCK) maximum value of 3000 ns, with a note

indicating that this only applies during the Program/Erase Suspend/Resume commands

DDR AC Characteristics

Added the tCSH CS# Active Hold Time (Relative to SCK) maximum value of 3000 ns, with a note

indicating that this only applies during the Program/Erase Suspend/Resume commands

Capacitance Characteristics

Added a Note 1, pointing users to the IBIS models for more details on capacitance

Physical Interface

Corrected pin 5 of the SOIC 16 Connection Diagram from NC to DNU

Corrected pin 13 of the SOIC 16 Connection Dig ram from DNU to NC

Replaced the WNF008 drawing with the WNG008 drawing

Updated the FAB024 drawing to the latest version

ASP Register

Corrected the statement “The programming time of the ASP Register is the same as the typical byte

programming time” to “The programming time of the ASP Register is the same as the typical page

programming time”

Persistent Protection Bits

Corrected the statement “Programming a PPB bit requires the typical byte programming time” to

“Programming a PPB bit requires the typical page programming time”

Register Read or Write

Corrected the statement “…the device remains busy and unable to receive most new operation

commands.” to “..the device remains busy. Under this condition, only the CLSR, WRDI, RDSR1,

RDSR2, and software RESET commands are valid commands.”

Page Program (PP 02h or 4PP 12h)

Removed the statement “If more than a page of data is sent to the device, previously latched data are

discarded and the last page worth of data (either 256 or 512 bytes) are programmed in the page. This is

the result of the device being equipped with a page program buffer that is only page size in length.”

Embedded Algorithm Performance

Tables

Updated the t_W WRR Write Time typical value from 100 ms to 140 ms and the maximum value from

200 ms to 500 ms

Updated t_PP Page Programming Time (256 bytes) maximum value from 550 µs to 750 µs

Added Note 3 and Note 4 to Table 10.7 to note shared performance values across other commands

Updated the t_ESL Erase Suspend Latency maximum value from 40 µs to 45 µs

Device ID and Common Flash Interface CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - EHPLC DDR table: corrected the data

(ID-CFI) Address Map

of offset 01h from 32h to 2Ah

Ordering Information

Added E0, E1, F0, F1, G0, and G1 as valid model numbers

Broke out the 2 character length model number decoder into separate characters to clarify format and

save space

Corrected the valid S25FLxxxSAGMFI model numbers from R0 and R1 to G0 and G1

Updated the Package Marking format to help identify speed differences across similar devices

Added G0 and G1 as valid model number combinations for SDR SOIC OPNs

Removed 20, 21, 30, and 31 as valid model numbers combinations for DDR BGA OPNs

Document Number: 001-98283 Rev. *I

Page 138 of 144

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