S25FL256SDSMHV200 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDSMHV200

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

3.3.14

QPP or QOR Address Input Cycle

The Quad Page Program and Quad Output Read commands send address to the memory only on IO0. The other IO signals are

ignored because the device must be in Quad mode for these commands thus the Hold and Write Protect features are not active. The

host keeps RESET# high, CS# low, and drives IO0.

For QPP the next interface state following the delivery of address is the Quad Input Cycle.

For QOR the next interface state following address is a Quad Latency Cycle if there are latency cycles needed or Quad Output

Cycle if no latency is required.

3.3.15

Quad Input Cycle - Host to Memory Transfer

The Quad I/O Read command transfers four address or mode bits to the memory in each cycle. The Quad Page Program command

transfers four data bits to the memory in each cycle. The host keeps RESET# high, CS# low, and drives the IO signals.

For Quad I/O Read the next interface state following the delivery of address and mode bits is a Quad Latency Cycle if there are

latency cycles needed or Quad Output Cycle if no latency is required. For Quad Page Program the host returns CS# high following

the delivery of data to be programmed and the interface returns to standby state.

3.3.16

Quad Latency (Dummy) Cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before

transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During

the latency cycles, the host keeps RESET# high, CS# low. The host may drive the IO signals during these cycles or the host may

leave the IO floating. The memory does not use any data driven on IO during the latency cycles. The host must stop driving the IO

signals on the falling edge at the end of the last latency cycle. It is recommended that the host stop driving them during all latency

cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency

cycles. This prevents driver conflict between host and memory when the signal direction changes. The memory does not drive the IO

signals during the latency cycles.

The next interface state following the last latency cycle is a Quad Output Cycle.

3.3.17

Quad Output Cycle - Memory to Host Transfer

The Quad Output Read and Quad I/O Read return data to the host four bits in each cycle. The host keeps RESET# high, and CS#

low. The memory drives data on IO0-IO3 signals during the Quad output cycles.

The next interface state continues to be Quad Output Cycle until the host returns CS# to high ending the command.

3.3.18

DDR Single Input Cycle - Host to Memory Transfer

The DDR Fast Read command sends address, and mode bits to the memory only on the IO0 signal. One bit is transferred on the

rising edge of SCK and one bit on the falling edge in each cycle. The host keeps RESET# high, and CS# low. The other IO signals

are ignored by the memory.

The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.

3.3.19

DDR Dual Input Cycle - Host to Memory Transfer

The DDR Dual I/O Read command sends address, and mode bits to the memory only on the IO0 and IO1 signals. Two bits are

transferred on the rising edge of SCK and two bits on the falling edge in each cycle. The host keeps RESET# high, and CS# low.

The IO2 and IO3 signals are ignored by the memory.

The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.

3.3.20

DDR Quad Input Cycle - Host to Memory Transfer

The DDR Quad I/O Read command sends address, and mode bits to the memory on all the IO signals. Four bits are transferred on

the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps RESET# high, and CS# low.

The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.

Document Number: 001-98283 Rev. *I

Page 22 of 144

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