S25FL128SDPMFVB10 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL128SDPMFVB10
Cypress Semiconductor
S25FL128SDPMFVB10 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
Table 5.5 AC Characteristics (Single Die Package, VIO 1.65V to 2.7V, VCC 2.7V to 3.6V)
Symbol
Parameter
Min
Typ
Max
Unit
FSCK, R
FSCK, C
PSCK
SCK Clock Frequency for READ, 4READ instructions
SCK Clock Frequency for all others (3)
SCK Clock Period
DC
DC
1/ FSCK
50 (6)
66 (6)
MHz
MHz
tWH, tCH
tWL, tCL
tCRT, tCLCH
tCFT, tCHCL
tCS
Clock High Time (4)
Clock Low Time (4)
Clock Rise Time (slew rate)
Clock Fall Time (slew rate)
CS# High Time (Read Instructions)
CS# High Time (Program/Erase)
45% PSCK
45% PSCK
0.1
0.1
10
50
ns
ns
V/ns
V/ns
ns
tCSS
CS# Active Setup Time (relative to SCK)
10
ns
tCSH
CS# Active Hold Time (relative to SCK)
3
3000 (5)
ns
tSU
Data in Setup Time
5
ns
tHD
Data in Hold Time
4
ns
tV
Clock Low to Output Valid
14.5 (2)
12.0 (3)
ns
tHO
tDIS
tWPS
tWPH
tHLCH
tCHHH
tHHCH
tCHHL
tHZ
tLZ
Output Hold Time
Output Disable Time
WP# Setup Time
WP# Hold Time
HOLD# Active Setup Time (relative to SCK)
HOLD# Active Hold Time (relative to SCK)
HOLD# Non Active Setup Time (relative to SCK)
HOLD# Non Active Hold Time (relative to SCK)
HOLD# enable to Output Invalid
HOLD# disable to Output Valid
2
0
20 (1)
100 (1)
5
5
5
5
ns
14
ns
ns
ns
ns
ns
ns
ns
14
ns
14
ns
Notes:
1. Only applicable as a constraint for WRR instruction when SRWD is set to a 1.
2. CL = 30 pF.
3. CL = 15 pF.
4. ±10% duty cycle is supported for frequencies 50 MHz.
5. Maximum value only applies during Program/Erase Suspend/Resume commands.
6. For Industrial Plus (-40°C to +105°C) and Extended (-40°C to +125°C) temperature range, all SCK clock frequencies are 5% slower than the Max values shown.
5.4.1
Clock Timing
Figure 5.8 Clock Timing
VIH min
VIO / 2
VIL max
PSCK
tCH
tCL
tCRT
tCFT
Document Number: 001-98283 Rev. *I
Page 33 of 144
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