S25FL128SDPMFVE10 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL128SDPMFVE10
Cypress Semiconductor
S25FL128SDPMFVE10 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
5.5 DDR AC Characteristics
Table 5.6 AC Characteristics — DDR Operation
Symbol
Parameter
66 MHz
80 MHz
FSCK, R
PSCK, R
tWH, tCH
tWL, tCL
tCS
tCSS
tCSH
tSU
tHD
tV
tHO
tDIS
tLZ
tO_SKEW
SCK Clock Frequency for DDR READ instruction
SCK Clock Period for DDR READ instruction
Clock High Time
Clock Low Time
CS# High Time (Read Instructions)
CS# Active Setup Time (relative to SCK)
CS# Active Hold Time (relative to SCK)
IO in Setup Time
IO in Hold Time
Clock Low to Output Valid
Output Hold Time
Output Disable Time
Clock to Output Low Impedance
First Output to last Output data valid time
Min
Typ
DC
15
45% PSCK
45% PSCK
10
3
3
2
2
0
0
0
Max
Min
Typ
66 (3)
DC
12.5
45% PSCK
45% PSCK
10
3
3
3000 (2)
1.5
1.5
6.5 (1)
1.5
1.5
8
8
0
600
Max
80 (3)
3000 (2)
6.5 (1)
8
8
600
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
Notes:
1. Regulated VCC range (3.0 - 3.6V) and CL =15 pF.
2. Maximum value only applies during Program/Erase Suspend/Resume commands.
3. For Industrial Plus (-40°C to +105°C) and Extended (-40°C to +125°C) temperature range, all SCK clock frequencies are 5% slower than the Max values shown.
5.5.1
DDR Input Timing
CS#
SCK
SI_or_IO
SO
Figure 5.14 SPI DDR Input Timing
tCS
tCSH
tCSH
tCSS
tCSS
tHD
tSU
tHD
tSU
MSB IN
LSB IN
Document Number: 001-98283 Rev. *I
Page 36 of 144
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