S25FL256SAGBFVB13 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SAGBFVB13

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor

S25FL256SAGBFVB13 Datasheet PDF : 144 Pages

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S25FL128S, S25FL256S

5.5.2

DDR Output Timing

Figure 5.15 SPI DDR Output Timing

CS#

SCK

SO_or_IO

tLZ

tHO

MSB

LSB

tCS

tDIS

SCK

IO0

IO1

Figure 5.16 SPI DDR Data Valid Window

PSCK

tCL

tCH

tO_SKEW

Slow

tOTT

Slow

IO2

IO3

Fast

IO_valid

Valid

tDV

Notes:

1. tCLH is the shorter duration of tCL or tCH.

2. tO_SKEW is the maximum difference (delta) between the minimum and maximum tV (output valid) across all IO signals.

3. tOTT is the maximum Output Transition Time from one valid data value to the next valid data value on each IO.

4. tOTT is dependent on system level considerations including:

a. Memory device output impedance (drive strength).

b. System level parasitics on the IOs (primarily bus capacitance).

c. Host memory controller input vIH and vIL levels at which 0 to 1 and 1 to 0 transitions are recognized.

d. As an example, assuming that the above considerations result a memory output slew rate of 2V/ns and a 3V transition (from 1 to 0 or 0 to 1) is required by the host,

the tOTT would be:

tOTT = 3V/(2V/ns) = 1.5 ns

e. tOTT is not a specification tested by Cypress, it is system dependent and must be derived by the system designer based on the above considerations.

5. The minimum data valid window (tDV) can be calculated as follows:

a. As an example, assuming:

i. 80 MHz clock frequency = 12.5 ns clock period

ii. DDR operations are specified to have a duty cycle of 45% or higher

iii. tCLH = 0.45*PSCK = 0.45x12.5 ns = 5.625 ns

iv. tO_SKEW = 600 ps

v. tOTT = 1.5 ns

b. tDV = tCLH - tO_SKEW - tOTT

c. tDV = 5.625 ns - 600 ps - 1.5 ns = 3.525 ns

Document Number: 001-98283 Rev. *I

Page 37 of 144

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