S25FL128SDPMFVB10 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL128SDPMFVB10
Cypress Semiconductor
S25FL128SDPMFVB10 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
7.3 ID-CFI Address Space
The RDID command (9Fh) reads information from a separate flash memory address space for device identification (ID) and
Common Flash Interface (CFI) information. See Device ID and Common Flash Interface (ID-CFI) Address Map on page 120 for the
tables defining the contents of the ID-CFI address space. The ID-CFI address space is programmed by Cypress and read-only for
the host system.
7.4 OTP Address Space
Each S25FL128S and S25FL256S memory device has a 1024-byte One Time Program (OTP) address space that is separate from
the main flash array. The OTP area is divided into 32, individually lockable, 32-byte aligned and length regions.
In the 32-byte region starting at address zero:
The 16 lowest address bytes are programmed by Cypress with a 128-bit random number. Only Cypress is able to program
these bytes.
The next 4 higher address bytes (OTP Lock Bytes) are used to provide one bit per OTP region to permanently protect each
region from programming. The bytes are erased when shipped from Cypress. After an OTP region is programmed, it can
be locked to prevent further programming, by programming the related protection bit in the OTP Lock Bytes.
The next higher 12 bytes of the lowest address region are Reserved for Future Use (RFU). The bits in these RFU bytes may
be programmed by the host system but it must be understood that a future device may use those bits for protection of a
larger OTP space. The bytes are erased when shipped from Cypress.
The remaining regions are erased when shipped from Cypress, and are available for programming of additional permanent data.
Refer to Figure 7.1, OTP Address Space on page 47 for a pictorial representation of the OTP memory space.
The OTP memory space is intended for increased system security. OTP values, such as the random number programmed by
Cypress, can be used to “mate” a flash component with the system CPU/ASIC to prevent device substitution.
The configuration register FREEZE (CR1[0]) bit protects the entire OTP memory space from programming when set to 1. This allows
trusted boot code to control programming of OTP regions then set the FREEZE bit to prevent further OTP memory space
programming during the remainder of normal power-on system operation.
Figure 7.1 OTP Address Space
32-byte OTP Region 31
32-byte OTP Region 30
32-byte OTP Region 29
.
When programmed to ‘0’
each lock bit protects its
.
related 32-byte region from
any further programming
.
...
Lock Bits 31 to 0
32-byte OTP Region 3
32-byte OTP Region 2
32-byte OTP Region 1
32-byte OTP Region 0
{ Contents of Region 0
Reserved Lock Bytes 16-byte Random Number
Byte 1F
Byte 10
Byte 0
Document Number: 001-98283 Rev. *I
Page 47 of 144
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